Conventional content addressable memory (CAM) has been implemented primarily using static random access memory (SRAM) cells. SRAM-based CAMs have received widespread use due to the high access speed of SRAM memory cells and the static nature of the cells. Furthermore, SRAM cells can be manufactured using a pure-logic type fabrication process, which is commonly used for non-memory circuit blocks.
In addition to random access memory (RAM) functions of writing and storing data, the CAM also searches and compares the stored data to determine if the data matches search data applied to the memory. When the newly applied search data matches the data already stored in the memory, a match result is indicated, whereas if the search and stored data do not match, a mismatch result is indicated. CAMs are particularly useful for fully associative memories such as look-up tables and memory-management units.
Many current applications utilise ternary CAMs, which are capable of storing three logic states. For example, the three logic states are logic ‘0’, logic ‘1’ and “don't care”. Therefore, such CAM cells require two memory cells to store the logic states, as well as a comparison circuit for comparing stored data wit search data provided to the CAM.
In ternary form, each conventional SRAM-based CAM memory cell comprises a regular six-transistor (6T) SRAM cells. Therefore, SRAM-based CAM cells typically use 12 transistors to implement two 6T SRAM cells. That is, each SRAM cell requires 2 p-channel transistors and 2 n-channel transistors in a cross-coupled inverter relationship and a further 2 n-channel transistors as access devices from the bit lines.
Furthermore, four additional transistors are required for each ternary CAM memory cell for implementing an exclusive NOR function for comparing the search data with the stored data. For ternary CAM cells, a-channel devices are typically used in the comparison circuit.
Previous approaches in the art store data in a main memory cell and mask data in a mask memory cell. The comparison circuit is then either enabled or disabled by the mask memory cell contents. Examples of memory cells implementing such an approach are illustrated by U.S. Pat. No. 6,154,384, issued to Nataraj et al. and U.S. Pat. No. 6,108,227 issued to Voelkel. Although this approach is functional from a circuit point of view, difficulty arises when attempting to layout the elements of the CAM cells. The main problem is a non-optimised layout of the CAM cell, which takes up more silicon area than desired.
DRAM-based CAMs have also been proposed in the art. DRAM cells are typically physically smaller than SRAM cells. Therefore, DRAM-based CAMs have the advantage of being able to store much more data than SRAM-based CAMs for a given area due to the much smaller CAM cell size. However, because of the dynamic nature of the DRAM cell, which is used to implement a DRAM-based CAM cell, such cells require regular refresh operations in order to maintain the data.
U.S. Pat. No. 6,188,594 issued to Ong describes a CAM cell using only n-channel transistors. The CAM cell uses only n-channel transistors. The size of the cell is significantly reduced since the p-channel transistors are eliminated. The cell size is further reduced by using dynamic storage rather ta static storage in the CAM cell. The dynamic CAM cell as described has as few as six transistors, and a compact layout is facilitated. However, as previously mentioned, dynamic cells require regular refresh operations in order to maintain the data and such refresh circuitry takes up additional silicon area.
Therefore, there is a need for an SRAM-based CAM cell that achieves a more efficient spatial layout than the prior art, while maintaining the static characteristic of the SRAM-based CAM cell.